Exploiting memory allocations in clusterised many‐core architectures

Exploiting Manycore Architectures for Parallel Data Stream Processing

7.4 Runtime memory optimization and GPU/manycore architectures

Manufacturing-time process (P) variations and runtime variations in voltage (V) and temperature (T) can affect a DRAM's performance (internal delays) severely. To counter the effects of these variations, DRAM vendors provide substantial design-time PVT margins to guarantee correct DRAM functionality under worst-case conditions. Unfortunately, with technology scaling these design margins have be...

7.4 Runtime memory optimization and GPU/manycore architectures

Manufacturing-time process (P) variations and runtime variations in voltage (V) and temperature (T) can affect a DRAM's performance (internal delays) severely. To counter the effects of these variations, DRAM vendors provide substantial design-time PVT margins to guarantee correct DRAM functionality under worst-case conditions. Unfortunately, with technology scaling these design margins have be...

Temperature-Aware Amdahl’s Law for Manycore Architectures

Small cores provide greater throughput per unit area and per watt when sufficient concurrency is available, motivating organizations with many simple cores. However, sufficient concurrency is often not available; even applications that can use many cores often have serial parts. Amdahl’s Law favors an asymmetric architecture and shows that one or more large, high-ILP cores are needed in these c...

Exploiting Hidden Non-uniformity of Uniform Memory Access on Manycore CPUs

As the rate of CPU clock improvement has stalled for the last decade, increased use of parallelism in the form of multiand many-core processors has been chased to improve overall performance. Current highend manycore CPUs already accommodate up to hundreds of processing cores. At the same time, these architectures come with complex on-chip networks for inter-core communication and multiple memo...